1. Field of the Invention
The present invention relates to semiconductor memory devices and methods of fabricating the same, and more particularly, to flash memory devices and methods of fabricating the same.
A claim of priority is made to Korean Patent Application No. 2004-111398, filed Dec. 23, 2004, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
Semiconductor memory devices that store data can be generally categorized as either volatile memory devices or nonvolatile memory devices. A volatile memory device will lose its stored data when no power is supplied to the device, whereas a nonvolatile memory device will retain its stored data when no power is supplied to the device. Accordingly, nonvolatile memory devices, for example, flash memory devices, are widely employed in mobile telecommunication systems, memory cards, and so forth.
A flash memory device comprises cell transistors for storing data, and a driving circuit for driving the cell transistors. The cell transistors are formed in a cell region of a semiconductor substrate while the driving circuit is formed in a peripheral circuit region of the semiconductor substrate. Typically, there are millions (or more) of the cell transistors formed in the cell region of the semiconductor substrate. A flash memory device can be classified as a NOR flash memory device or a NAND flash memory device based on the structure of its cell array. The cell array structure of the NOR flash memory device allows random access to cell transistors. The cell array structure of the NAND flash memory device is defined by strings of cell transistors in the cell region of the device. Each string is composed of an even number of cell transistors arranged and connected in a line of an active region. For example, each string may be composed of thirty-two cell transistors.
FIG. 1 is a cross-sectional view illustrating a conventional NAND flash memory device, where the plane of cross-section is perpendicular to the word line.
Referring to FIG. 1, an isolation layer 7 is formed in a predetermined region of a semiconductor substrate 1. The isolation layer 7 defines (i.e., separates) first and second active regions 1A and 1B, which are parallel to each other. A control gate electrode 13 is formed to cross over the first and second active regions 1A and 1B. The control gate electrode 13 acts as a word line.
Floating gates 10A and 10B are interposed between the control gate electrode 13 and the active regions 1A and 1B, respectively. That is, the first floating gate 10A is interposed between the control gate electrode 13 and the first active region 1A, and the second floating gate 10B is interposed between the control gate electrode 13 and the second active region 1B. The floating gates 10A and 10B are insulated from the control gate electrode 13 by an inter-gate dielectric layer 11. Furthermore, the floating gates 10A and 10B are insulated from the active regions 1A and 1B by a tunnel dielectric layer 3. In addition, the control gate electrode 13 has a control gate extension 13A interposed between the floating gates 10A and 10B.
Cell transistors CE1 and CE2 are formed at intersections of the control gate electrode 13 and the active regions 1A and 1B, respectively. That is, the first cell transistor CE1 is formed at an intersection of the control gate electrode 13 and the first active region 1A, and the second cell transistor CE2 is formed at an intersection of the control gate electrode 13 and the second active region 1B.
A top surface of the isolation layer 7 is typically positioned higher than bottom surfaces of the floating gates 10A and 10B as shown in FIG. 1. In this case, parasitic coupling capacitors, which employ the isolation layer 7 as a dielectric layer, may be formed between the floating gates 10A and 10B. For example, a coupling capacitor C1 is formed between the first and second floating gates 10A and 10B, which each have a side that faces the other and have the isolation layer 7 interposed in between, as shown in FIG. 1.
The capacitance of the coupling capacitor C1 increases as a distance between the floating gates 10A and 10B decreases. In addition, the capacitance of the coupling capacitor C1 increases as an effective cross-sectional area facing between the floating gates 10A and 10B increases. That is, as the degree of integration of the NAND flash memory device increases, the coupling capacitance between the floating gates 10A and 10B (i.e., the inter-floating gate coupling capacitance) increases. In this case, when the first cell transistor CE1 is selectively programmed, electrons are injected into the first floating gate 10A to change an electric potential of the first floating gate 10A, and an electric potential of the second floating gate 10B adjacent to the first floating gate 10A also changes due to the coupling capacitor C1. As a result, a threshold voltage of the second cell transistor CE2 changes. Accordingly, a string which includes the second cell transistor CE2 may malfunction in a read operation mode.
In order to improve the coupling capacitor C1, methods of extending the control gate extension 13A to a level lower than bottom surfaces of the floating gates 10A and 10B have been researched.
A NAND flash memory device associated with the inter-floating gate coupling capacitance and a method of fabricating the same are disclosed by Iguchi et al. in “Semiconductor device and method of manufacturing the same” (U.S. patent publication No. 2004/0099900 A1). According to Iguchi et al., a plurality of control gate electrodes is formed to cross over a plurality of parallel active regions, and floating gates are interposed between the control gate electrodes and the active regions. The floating gates are insulated from the active regions by a tunnel dielectric layer. Each of the control gate electrodes has extensions which penetrate an isolation layer between the floating gates and are lower than top surfaces of the active regions.
However, a process of partially etching the isolation layer to be removed is required in order to form the extensions. The process of partially etching the isolation layer includes a wet etching process and a dry etching process. It is very difficult to control an etching depth when using the wet etching process, and thus the process may result in harm to the NAND flash memory device. For example, when over-etching occurs, the tunneling dielectric layer is damaged. The dry etching process uses the floating gates as etch masks. When using the dry etching process, the floating gates and the tunneling dielectric layer may be damaged due to plasma.